Wednesday 13 February 2019

R&D - Understanding SMPTE ST 2110 - ST 2110-21

Part 6 of Understanding SMPTE ST 2110 Virtual Course.

The SMPTE ST 2110 suite of standards regulate the transport of media essence over an IP network.

For professional live TV production, this transport has to be low latency and comparable to the latency of the current SDI infrastructure.

SMPTE ST 2110-21 parametric modules for packet delivery timing characteristics

Senders

A Sender can capture, create and playback video, audio and data essence. This is packetised and sent to the ingress interface for transport over a connected IP link.

Delays could occur in this process
There are two main groups of senders
Hardware and Software senders

Receivers

Receivers receive packets from the IP network from the egress interface which is placed in a buffet to compensate for out of order packets, and packet delay variation (PVD) just is also known as network jitter.

Once sufficient packets for a meaningful output are buffered the essence is unpacked from the packets and passed on for display, processing or output (this process also creates some latency, just like the receiver) and care has to be taken in the design of receivers to keep that latency to a minimum.

Switch

One or more IP switches are at the heart of the Live TV production infrastructure. Switch designs and architecture vary from vendor to vendor.

A switch is a network device with multiple receivers and senders; multiple ports can either act as ingress or egress interface. The ports are connected to ingress or egress queues where network packets can be buffered and queued for switching. The Arbiter managers the queues and determines when the packet from a specific queue can enter the queue. This is important to avoid coalition in the switching fabric if two queues send packets to the same output.

The switching fabric which is usually implemented as ASIC (Application Specific Integrated Circuit) routes the packets from the egress queue to the egress port. The forwarding Engine performs a lookup of route addresses based on the packet header information.

The switch fabric speed is a theoretical maximum throughput of a switch which can be is the single digit microsecond range, which can accumulate in a multi-switch environment.

Network Devices

Hardware
Field Programmable Gate Array (FPGA) is an integrated circuit which allows users to configure them for their use after they are produced. An FPGA can be reconfigured in a matter of minutes to switch from one application to another.
FPGA's offer better performance than software solutions.

The effects of network devices on transport traffic

Latency behaviour and packet spacing during transport over the IP network depend on the network device.
Bursty network traffic can occur
Non-deterministic latency variations
Buffers remedy latency and bursty traffic
Buffers can create latency itself
Latency can accumulate, this will affect the system timing (in the case of SMPTE ST 2110, its PTP)

Packet Delay Variation (Jitter)
This occurs when packets are sent out in an even manner but received at different delay variation is the image below.

Packet Loss
Packet losses are bound to occur on any give network setup.


Non-Blocking Network Traffic
This is a traffic mode where packets come from the sender, goes straight through the switch queue and then to the receiver; This is the simplest form of network traffic.

Bursty Network Traffic
In bursty network, the traffic flow is quick, leading to overflows in the switch queue and buffer, which will eventually lead to packet loss.

Why Traffic Shaping?

Traffic shaping was designed to schedule packet flows at regular intervals into the network, to avoid overflowing the switch queue or receiver buffer.

Some of the benefits of traffic shaping include,
To ensure a low latency transport of uncompressed active video over IP and provide interoperability with SDI interfaces.
To provide deterministic network behaviour when transporting IP packets, align the signal to the overall system synchronisation, which will optimise video switching.
and support for COTS switches


SMPTE ST 2110-21 defines the maximum capacity of a buffer as Cmax and the actual buffer fullness at a given time or instantaneous fullness as Cinst.

Packet Read Schedule (PRS)
Progressive PRS (Linear)
Progressive PRS (Gapped)
Interlaced PRS (Gapped)

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